1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel device configuration and manufacturing process to provide silicide gate and mesa contact regions to reduce gate resistance and source contact resistance and body contact resistance of a MOSFET power device.
2. Description of the Prior Art
With the advent of high efficiency metal oxide semiconductor (MOS) gate devices for hand held electronics power-switching applications leads to a more stringent requirement to further reduce the on-resistance of the MOSFET device. In order to satisfy this requirement, several configurations have been disclosed in attempt to reduce the resistance of a MOSFET device.
In U.S. Pat. No. 6,855,601, Gajda discloses a device configuration for reducing the gate resistance for a power semiconductor device with trenched gates. In this device the trenched gate protrudes upwardly from the trench in the form of a silicide upstanding part which is of a metal silicide material between its top and sidewalls above the level of the body surface. As shown in FIG. 1A, the gate dielectric layer at least adjacent to the channel-accommodating region is separated from the metal silicide material by at least the semiconductor part of the gate and by the protrusion of the silicide part upward above the level of the body surface. The protrusion of the upstanding silicide part above the level of the body surface permits the inclusion of a substantial volume of silicide to reduce gate resistance without impacting other device performing features. In the device disclosed by Gajda, the protrusion of the silicide upstanding part of the gate above the level of the body surface may be larger than half the width of the trench. This protrusion may typically be as large as the width of the trench or larger, for example several times larger than the width of the trench. Implementation of the special device configuration and manufacturing processes reduction of gate resistance is accomplished. However, the invention as disclosed requires extensive process development and integration complexity. Furthermore, the invention as disclosed is not yet able to provide an effective solution to address the issues of reducing the source contact resistance and body contact resistance.
In a published paper entitled “A High Performance Self-Aligned UMOSFET with a Vertical Trench Contact Structure” (IEEE Transactions on Electronic Devices, Vol. 41, No. 3, May 1994), Matsumoto et al. disclose a configuration to reduce the source contact resistance. As shown in FIG. 1B, the configuration involves the opening of vertical trench contact to the source. Such device configuration may be useful for addressing the issue of scaling trench MOSFET so that the reduced source contact area would not limit device pitch reduction. However it does not provide a reduced source contact resistance as low as that is commonly demanded by many different low resistance applications. The disclosed UMOSFET in the paper is also not effective for reducing the gate resistance.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.